Guideposts: Chinese Semiconductor Maker's Latest Triumph Over U.S. Sanctions | | by George Gilder and Dr. Robert Castellano
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Result: China keeps proving the consensus wrong, and the sanctions counterproductive by making elite chips anyway.
Okay, gird your loins, technical discussion incoming:
The most elite, most capable logic chips, broadly speaking, are those that can pack the most transistors into a given area, usually measured by millions of transistors per square millimeter: (MTr/mm²).
Progressively more powerful generations have been designated as "14nm," "10nm," "7nm," "5nm," "3nm," and now "2nm." (Although nm. stands for nanometer, it's been many years since these designations corresponded closely to actual transistor dimensions, thus the quotation marks. See Table 1)
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Click here to see how anyone can profit fast. | | | Translating into circuit density, a "7nm" chip will include very roughly 100 MTr/mm², though the actual number can vary by 20% or more. A "5nm" chip made by Taiwan Semiconductor (NYSE: TSM) includes approximately 170 MTr/mm², Intel's (NASDAQ: INTC) version includes approximately 160 MTr/mm².
Starting with 7nm, elite chips have required "extreme ultraviolet photolithography" (EUV) to etch the tiny circuits required for these super-dense chips. ASML makes the only machine in the world capable of doing that job. The latest generation, the TWINSCAN EXE:5000, sells for about $370 million. That's the machine the United States forbids ASML from selling to Chinese companies.
Having arm-twisted the Dutch into complying with the ban, the sanction-makers duly patted themselves on the back. Thanks to their heroic efforts, Chinese chipmakers would never get to 7nm!!!!!!
Except they did, quickly.
By July 2022, China's largest chip manufacturer, Semiconductor Manufacturing International Corporation, SMIC, (HKG: 0981), was making a "7nm" chip. This was done without EUV, using only ASML's less capable DUV (deep ultraviolet) machines, which are exempt from sanctions. Cue seismic tremor.
And now for the earthquake: SMIC has just released its first 5nm prototype. If 7nm was thought to be impossible without ASML's EUV equipment, 5nm was thought to be totally super-mega-impossible.
Is 3nm next?
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Get Immediate Access. | | | SMIC has been able to reach "7nm" and now "5nm" using only "deep ultraviolet" lithography by a jury-rigged process. EUV photolithography speeds and simplifies the process of laying down a circuit pattern because it can do so in a single exposure even for extremely fine features. To get to 7nm and now 5nm with DUV requires multiple patterning steps such as self-aligned double or quadruple patterning (SADP, SAQP). These multi-steps are expensive and multiply the chance for error, thus reducing yield, or how many good chips come off a wafer. Table 2 outlines these differences.
DUV-based 5nm production has a significantly higher mask count (for mask, think "stencil" at nanometer dimensions) and patterning cost. Aligning multiple exposures is complicated and error prone leading to higher defect rates and lower yield compared to EUV-based production. Also, these inferior processes mean the transistors need more space. The density of SMIC's 5nm mode appears to be just more than half of TSM's, or 90 MTr/mm² vs. 170 MTr/mm².
SMIC's DUV processes, however, will almost inevitably improve, probably by quite a lot, as volume mounts. Process is where the learning curve, now documented across thousands of industrial and business processes, reigns most imperiously. The bit by bit, step by step, largely unpredictable and sometimes barely conscious refinement of production processes manifests itself in a 20-30% reduction in costs per doubling of accumulated volume. And since we're counting transistors, those doublings come mighty quickly.
Using DUV rather than EUV for elite modes was not the course the Chinese would have chosen. But being forced to do so, and having now demonstrated that it can be done, expect DUV process productivity increasingly to rival what EUV does today.
Naturally, EUV will ride the learning curve as well, which is why TSM is on the brink of producing 2nm chips at commercial scale. Still, SMIC should probably be sending love notes or at least flowers to the geniuses who came up with sanctions as a way to cripple Chinese engineering.
Are you asking yourself the obvious next question: what does all this mean for ASML and its stockholders. Subscribers to our Gilder's Technology Report will learn that later this week.
Sincerely,
George Gilder, Richard Vigilante, Steve Waite, John Schroeter, and Robert Castellano
Editors, Gilder's Guideposts, Technology Report, Technology Report Pro, Moonshots, and Private Reserve | | About George Gilder:
 George Gilder is the most knowledgeable man in America when it comes to the future of technology and its impact on our lives. He’s an established investor, bestselling author, and economist with an uncanny ability to foresee how new breakthroughs will play out, years in advance. George and his team are the editors of Gilder Technology Report, Gilder Technology Report Pro, Moonshots and Private Reserve. | | | | | |
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